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1- wire is a registered trademark of maxim integrated products, inc. 1 of 12 features ? unique, factory - lasered and tested 64 - bit registration number (8 - bit family code plus 48 - bit serial number plus 8 - bit crc tester); guaranteed no two parts alike ? standby current <1a ? built - in multidrop controller enables multiple ds 2411s to reside on a common 1- wire ? network ? multidrop compatible with other 1 - wire products ? 8- bit family code identifies device as ds2411 to the 1 - wire master ? low - cost tsoc, sot23 - 3, and flip -chip surface - mount packages ? directly connects to a single - port pin of a microprocessor and communicates at up to 15.4kbps ? overdrive mode boosts communication speed to 125kbps ? operating range: 1.5v to 5.25v, - 40c to +85c pin description name pin sot23 tsoc flip chip i/o 1 2 a1 v cc 2 6 b2 gnd 3 1 b1 n.c. 3, 4, 5 a2 pin configuration 1 2 3 sot23 - 3, top view tsoc, top view 1 2 3 6 5 4 flip chip, top view with laser mark, contacts not visible. rrd = revision/date - 1rrd a b 1 2 ordering information part temp range pin - package ds2411r+t&r -40 c to +85 c 3 sot23 -3 ds2411p+ -40 c to +85 c 6 tsoc ds2411p+t&r -40 c to +85 c 6 tsoc ds2411x -40 c to +85 c 4 flip chip * + denotes a lead(pb) - free/rohs - compliant package. t&r = tape and reel. * the ds2411x is rohs qualified and c omes in tape and reel . description the ds2411 silicon serial number is a low - cost, electronic registration number with external power supply. it provides an absolutely unique identity that can be determined with a minimal electronic interface (typically, a single port pin of a microcontroller). the d s2411s registration number is a factory - lasered, 64 - bit rom that includes a unique 48 - bit serial number, an 8 - bit crc, and an 8 - bit family code (01h). data is transferred serially through the maxim 1- wire protocol. the external power supply is required, extending the operating voltage range of the device b elow typical 1- wire devices. ds2411 silicon serial number with v cc input 19 - 6131; rev 1 1 /11 downloaded from: http:///
ds2411 2 of 12 absolute maximum ratings i/o voltage to gnd - 0.5v to +6v v cc voltage to gnd - 0.5v to +6v i/o, v cc current 20ma operating temperature range - 40c to +85c junction temperature +150c storage temperature range - 55c to +125c lead temperature (tsoc, sot23 - 3 only ; soldering , 10s) +300c solde ring temperature (reflow) tsoc, sot -23-3 flip chip +260c +240c this is a stress rating only and functional operation of the device at these or any other c onditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating c onditions for extended periods of time may affect reliability. electrical characteristics (v cc = 1.5v to 5.25v; t a = - 40 c to +85 c.) parameter symbol conditions min max units o perating temperature t a (note 1) -40 +85 c supply voltage v cc (note 1) 1.5 5.25 v 1- wire pullup v cc = v pup (note 1) 1.5 5.25 v i/o pin general data 1- wire pullup resistance r pup (notes 1, 2) 0.3 2.2 k ? power - up delay t pwrp v cc stable to first 1- wire command (notes 1, 3) 1200 s input capacitance c io (note 3) 100 pf input load current i l 0v v(i/o) v cc -1 +1 a standby supply current i ccs v(i/o) v il , or v(i/o) v ih 1 a active supply current i cca 100 a high - to - low switching threshold v tl (notes 3, 4, 5) 0.4 3.2 v input low voltage v il (note 1) 0.30 v input high voltage v ih (note 1) v cc - 0.3 v low - to - high switching threshold v th (notes 3, 4, 6) 0.75 3.4 v switching hysteresis v hy (notes 3, 7) 0.18 v output low voltage at 4ma v ol (note 8) 0.4 v rising edge holdoff t reh standard speed (note 9, 3) 1.25 5 s overdrive speed (note 9, 3) 0.5 2 recovery time t rec standard speed, r pup = 2.2k ? (note 1) 5 s overdrive speed, r pup = 2.2k ? (note 1) 2 overdrive speed, directly prior to reset pulse; r pup = 2.2k ? (note 1) 5 downloaded from: http:///
ds2411 3 of 12 parameter symbol conditions min max units timeslot duration t slot standard speed 65 s overdrive v cc 2.2v 8 overdrive v cc 1.5v 10 i/o pin, 1 -w ire reset, presence dete ct cycle reset low time t rstl standard speed 480 640 s overdrive speed 60 80 presence - detect high time t pdh standard speed 15 60 s overdr ive v cc 2.2v 2 6 overdrive v cc 1.5v 2 8.5 presence - detect low time t pdl standard speed 60 240 s overdrive v cc 2.2v 8 24 overdrive v cc 1.5v 8 30 presence - detect fall time t fpd standard speed (note 10, 3) 0.4 8 s overdrive speed ( note 10, 3) 0.05 1 presence - detect sample time t msp standard speed (note 1) 60 75 s overdrive v cc 2.2v (note 1) 6 10 overdrive v cc 1.5v (note 1) 8.5 10 i/o pin, 1 - wire write write - 0 low time t w0l standard speed (notes 1, 11, 13) 60 120 s overdrive v cc 2.2v (notes 1, 11, 13) 6 16 overdrive v cc 1.5v (notes 1, 11, 13) 8 16 write - 1 low time t w1l standard speed (notes 1, 11, 13) 5 15 s overdrive speed (notes 1, 11, 13) 1 2 i/o pin, 1 - wire read read low time t rl standard speed (notes 1, 12) 5 15 - s overdrive speed (notes 1, 12) 1 2 - read sample time t msr standard speed (notes 1, 12) t rl + 15 s overdrive speed (notes 1, 12) t rl + 2 note 1: system requirement. note 2: maximum allowab le pullup resistance is a function of the number of 1 - wire devices in the system and 1 - wire recovery times. the specified value here applies to systems with on ly one device and with the minimum 1 - wire recovery times. for more heavily loaded systems, an act ive pullup such as that found in the ds2480b may be required. minimum allowable pullup resistance is slightly greater than the value necessary t o produce the absolute maximum current (20ma) during 1 - wire low times at v pup = 5.25v assuming v ol = 0v. note 3: not production tested. note 4: v tl and v th are functions of v cc and temperature. the v th and v tl maximum specifica - tions ar e valid at v cc = 5.25v. in any case, v tl < v th < v cc . note 5: voltage below which during a falling edge on i/o, a logic 0 is dete cted. note 6: voltage above which during a rising edge on i/o, a logic 1 is detected. note 7: after v th is crossed during a rising edge on i/o, the voltage on i/o has to drop by v hy to be detected as logic 0. note 8: the i - v characteristic is linear fo r voltages less than 1v. downloaded from: http:///
ds2411 4 of 12 note 9: the earliest recognition of a negative edge is possible at t reh after v th has been reached on the previous edge. note 10: interval during the negative edge on i/o at the beginning of a presence - detect pulse between the time at which the voltage is 90% of v pup and the time at which the voltage is 10% of v pup . note 11: in figure 7 represents the time required for the pullup circuitry to pull the vol tage on i/o up v il to v th . the actual maximum duration for the master to pul l the line low is t w1lmax + t f - and t w0lmax + t f - , respectively. note 12: in figure 7 represents the time required for the pullup circuitry to pull the vo ltage on i/o up from v il to the input - high threshold of the bus master. the actual maximum dur ation for the master to pull the line low is t rlmax + t f . note 13: interval begins when the voltage drops below v tl during a negative edge on i/o and ends when the voltage rises above v th during a positive edge on i/o. operation the ds2411s registration number is accessed through a single data line. the 48 - bit serial number, 8 - bit family code, and 8 - bit crc are retrieved using the maxim 1- wire protocol. this protocol defines bus transactions in terms of the bus state during specified time slots t hat are bus - master - generated falling edges on the i/o pin. all data is read and written least significant b it first. the device requires a delay between v cc power - up and initial 1 - wire communication, t pwrp (1200 s). during this time the device may issue pres ence - detect pulses. 1- wire bus system the 1 - wire bus has a single bus master and one or more slaves. in all in stances, the ds2411 is a slave device. the bus master is typically a microcontroller . the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1 - wire signaling (signal type and timing). hardware configuration the 1 - wire bus has a single data line, i/o. it is important that each device on th e bus be able to drive i/o at the appropriate time. to facilitate this, each device has an open - drain or three - state output. the ds2411 has an open - drain output with an internal circuit equivalent to that shown in f i gure 3. the bus master can have the same equivalent circuit. if a bidirectional pin is not available on the master, separate output and input pins can be connected together. the bus requires a pul lup resistor at the master end of the bus, as shown in figur e 4. a multidrop bus consists of a 1 - wire bus with multiple slaves attached. the 1 - wire bus has a maximum data rate of 15.4kbps in standard speed and 125kbps i n overdrive. the idle state for the 1 - wire bus is high. if a transaction needs to be suspended for any reason, i/ o must remain high if the transaction is to be resumed. if the bus is pull ed low, slave devices on the bus will interpret the low as either a timeslot, or a reset depending on the durati on. figure 1. ds2411 registration number msb ls b 8-bit crc code 48 - bit serial number 8- bit family code (01h) msb lsb msb lsb msb lsb downloaded from: http:///
ds2411 5 of 12 figure 2. 1 - wire crc generator x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1st stage 2nd stage 3rd stage 4th stage 6th stage 5th stage 7th stage 8th stage input data figure 3. ds2411 equivalent circuit 100 mosfet rx tx v cc i/o - 1 a i l 1a ground figure 4. bus master circuit open -drain port pin bus master ds5000 or 8051 equivalent v cc to ds2411 rx tx r pup i/o to ds2411 ground to ds2411 r pup must be between 0.3 k ? and 2.2 k ? . the optimal value depends on the 1-wire communication speed and the bus load characteristics. downloaded from: http:///
ds2411 6 of 12 transaction sequence the communication sequence for accessing the ds2411 through the 1 - wire bus is as follows: ? initialization ? rom function command ? read data init ialization all transactions on the 1 - wire bus begin with an initialization sequence. the initialization seq uence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets th e bus master know that the ds2411 is on the bus and is ready to operate. for more details, see the 1- wire signaling section. rom function commands once the bus master has detected a presence, it can issue one of the three rom funct ion commands. all rom fu nction command codes are 1 byte long. a list of these commands follo ws (see the flowchart in figure 5). read rom [33h] this command allows the bus master to read the ds2411s 8 - bit family code, unique 48 - bit serial number, and 8 - bit crc. this command sho uld only be used if there is a single slave device on the bus. if more than one slave is present on the bus, a data collision results whe n all slaves try to transmit at the same time (open drain produces a wired - and result), and the resulting registration number read by the master will be invalid. search rom [f0h] when a system is initially brought up, the bus master might not know t he number of devices on the 1- wire bus or their registration numbers. by taking advantage of the wir ed - and property of the b us, the master can use a process of elimination to identify the registration nu mbers of all slave devices. for each bit of the registration number, starting with the least significan t bit, the bus master issues a triplet of time slots. on the first slot, e ach slave device participating in the search outputs the true value of i ts registration number bit. on the second slot, each slave device partic ipating in the search outputs the complemented value of its registration number bit. on the third slot, the mast er writes the true value of the bit to be selected. all slave devices that do not match the bit written by the master stop participating in the search. if both of the read bits are zero, the master knows that sla ve devices exist with both states of the bit . by choosing which state to write, the bus master branches in the ro mcode tree. after one complete pass, the bus master knows the registration number of a single devi ce. additional passes identify the registration numbers of the remaining devices. refer t o app note 187: 1- wire search algorithm for a detailed discussion, including an example. overdrive skip rom [3ch] this command causes all overdrive - capable slave devices on the 1 - wire network to enter overdrive speed (od = 1). all communication following this command has to occur at overdrive speed until a reset pulse of minimum 480 s duration resets all devices on the bus to regular speed (od = 0). to subsequently address a specific overdrive - supporting device, a reset pulse at overdrive speed has to be issued followed by a read rom or search rom command sequence. overdrive sp eeds up the time for the search process. downloaded from: http:///
ds2411 7 of 12 figure 5. rom functions flow chart y n n ds2411 tx crc byte ds2411 tx serial number (6 bytes) ds2411 tx family code (1 byte) y n 33h read rom command? bit 63 match? ds2411 tx bit 0 ds2411 tx bit 0 master tx bit 0 ds2411 tx bit 1 ds2411 tx bit 1 master tx bit 1 ds2411 tx bit 63 ds2411 tx bit 63 master tx bit 63 bit 1 match? bit 0 match? y y n n f0h search rom command? y bus master tx rom function command ds2411 tx presence pulse od reset pulse ? n y od = 0 bus master tx reset pulse 3ch od skip command? od = 1 y n downloaded from: http:///
ds2411 8 of 12 1- wire signaling the ds2411 requires strict protocols to ensure data int egrity. the protocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. except for the presence pulse the bus master initiates all these s ignals. the ds2411 can communicate at two different speeds: standard speed and overdrive speed. if not explic itly set into the overdrive mode, the ds2411 will communicate at standard speed. while in ov erdrive mode the fast timing applies to all waveforms. to get from idle to active, the voltage on the 1 - wire line needs to fall from v pup below the threshold v tl . to get from active to idle, the voltage needs to rise from v ilmax past the threshold v th . the voltage v ilmax is relevant for the ds2411 when determining a logical level, but no t for triggering any events. the initialization sequence required to begin any communicati on with the ds2411 is shown in figure 6. a reset pulse followed by a presence pulse indicates the ds2411 is ready t o receive data, given the correct rom and memory function command. in a mixed population n etwork, the reset low time t rstl needs to be long enough for the slowest 1 - wire slave device to recognize it as a reset pulse. if the bus master uses slew - rate control on the falling edge, it must pull down the line for t rstl + t f to compensate for the edge. a t rstl duration of 480s or longer will exit the overdrive mode returning the devic e to standard speed. if the ds2411 is in overdrive mode and t rstl is no longer than 80s, the device will remain in overdrive mode. after the bus master has released the line it goes into receive mode (rx ). now, the 1 - wire bus is pulled to v pup via the pullup resistor or, in case of a ds2480b driver, by active circuit ry. when the threshold v th is crossed, the ds2411 waits for t pdh and then transmits a presence pulse by pulling the line low for t pdl . to detect a presence pulse, the master must test the logical state of the 1 - wire line at t msp . the t rsth window must be at least the sum of t pdhmax , t pdlmax , and t recmin . immediately after t rsth is expired, the ds2411 is ready for data communication. in a mixed popula tion network, t rsth should be extended to minimum 480s at standard speed and 48s at overdrive speed to acco mmodate other 1 - wire devices. read/write time slots data communi cation with the ds2411 takes place in time slots that carry a single bit each. write time slots transport data from bus master to slave. read time - slots transfer data from slave to master. the definitions of the write and read time slots are illustrated in figure 7. all communication begins with the master pulling the data line lo w. as the voltage on the 1 - wire line falls below the threshold v tl , the ds2411 starts its internal timing generator that determines wh en the data line will be sampled during a wr ite time slot and how long data will be valid during a read time slot. master to slave for a write -one time slot, the voltage on the data line must have crossed the v thmax threshold after the write - one low time t w1lmax is expired. for a write - zero time s lot, the voltage on the data line must stay below the v thmin threshold until the write - zero low time t w0lmin is expired. for most reliable communication the voltage on the data line should not exceed v ilmax during the entire t w0l window. after the v thmax t hreshold has been crossed, the ds2411 needs a recovery time t rec before it is ready for the next time slot. downloaded from: http:///
ds2411 9 of 12 initialization procedure figure 6. reset and presence pulse read/write timing diagram figure 7a. write - one time slo t figure 7b. write - zero time slot figure 7c. read - data time slot downloaded from: http:///
ds2411 10 of 12 slave to master a read -data time slot begins like a write - one time slot. the voltage on the data line must remain below v tlmin until the read low time t rl is expired. during the t rl window, when responding with a 0, the ds2411 will start pulling the data line low; its internal timing genera tor determines when this pull -down ends and the voltage starts risi ng again. when responding with a 1, the ds2411 will not hold the data li ne low at all, and the voltage starts rising as soon as t rl is over. the sum of t rl + (rise rime) on one side and the internal timing generator of the ds24 11 on the other side defi ne the master sampling window (t msrmin to t msrmax ) in which the master must perform a read from the data line. for most reliable communication, t rl should be as short as permissible and the master should read close to but no later than t msrmax . after reading from the data line, the master must wait until t slot is expired. this guarantees sufficient recovery time t rec for the ds2411 to get ready for the next time slot. improved network behavior in a 1 - wire environment, line termination is possible only du ring transients controlled by the bus master (1 - wire driver). 1 - wire networks therefore are susceptible to noise of various origins. d epending on the physical size and topology of the network, reflections from end poi nts and branch points can add up or can cel each other to some extent. such reflections are visible as glitches or r inging on the 1 - wire communication line. a glitch during the rising edge of a time slot can caus e a slave device to lose synchronization with the master and, as a consequence, resu lt in a search rom command coming to a dead end. for better performance in network applications, the ds2411 uses a new 1 - wire front end, which makes it less sensitive to noise and also reduces the magni tude of noise injected by the slave device itself. t he 1 - wire front end of the ds2411 differs from traditional slave devices in four characteristics. 1) the falling edge of the presence pulse has a controlled slew rate. this prov ides a better match to the line impedance than a digitally switched transistor, c onverting the high frequency ringing known from traditional devices into a smoother low - bandwidth transition. the slew rate control is specified by the parameter t fpd , which has different values for standard and overdrive speed. 2) there is additional low -pa ss filtering in the circuit that detects the falling edge at t he beginning of a time slot. this reduces the sensitivity to high - frequency noise. as a consequence, the duration of the setup time t su at standard speed is larger than with traditional devices. this additional filtering does not apply at overdrive speed. 3) there is a hysteresis at the low - to - high switching threshold v th . if a negative glitch crosses v th but doesnt go below v th - v hy , it will not be recognized (figure 8, case a). the hysteresis is effecti ve at any 1 - wire speed. 4) there is a time window specified by the rising edge hold - off time t reh during which glitches will be ignored, even if they extend below v th - v hy threshold (figure 8, case b, t gl < t reh ). deep voltage droops or glitches th at appear late after crossing the v th threshold and extend beyond the t reh window cannot be filtered out and will be taken as beginning of a new tim e slot (figure 8, case c, t gl t reh ). the duration of the hold - off time is independent of the 1 - wire speed. only devices which have the parameters t fpd , v hy and t reh specified in their electrical characteristics use the improved 1 - wire front end. downloaded from: http:///
ds2411 11 of 12 noise suppression scheme figure 8 v pup v th v hy 0v t reh t gl t reh t gl case a case c case b crc generation to validate the registration number transmitted from the ds2411, t he bus master can generate a crc value from the 8 - bit family code and unique 48 - bit serial number as it is received. if the crc matches the last 8 bits of the registration number, the transmission is error f ree. the equivalent polynomial function of this crc is: crc = x 8 + x 5 + x 4 + 1. for more information on generating crc values see application note 27 . custom ds2411 customization of a portion of the unique 48 - bit serial number by the customer is available. maxim will register and assign a specific customer id in the 12 most significant b its of the 48 - bit field. the next most significant bits are selectable by the customer as a starting value, a nd the least significant bits are non - selectable and will be automatically incremented by one. certain quantities and conditio ns apply for these custom parts. contact your maxim sales representative for more information. package information for the latest package outline information and land p atterns (footprints), go to www.maxim - ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings m ay show a different suffix character, but the drawing pert ains to the package regardless of rohs status. package type package code outline no. land pattern s ot23 -3 u3+3 21-0051 90-0179 6 tsoc d6+1 21-0382 90-0321 4 flip chip bf411-1 21-0282 refer to 21-0282 downloaded from: http:///
ds2411 12 of 12 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely em bodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 ? 2011 maxim int egrated products maxim is a registered trademark of maxim integ rated products, inc. revision history revision date description pages changed 020703 initial release 052003 corrected the flip chip pin configuration. 1 section 1- wire signaling rewritten. 8, 10 added s ection improved network behavior . 10, 11 122106 added f lip c hip top marking and url to package outline drawing . added sot23 - 3 and tsoc lead - free part numbers to ordering information . 1 11/11 updated ordering information, lead temperature, soldering temperatur e. 1, 2 in the electrical characteristics table, applied note 11 to the t w0l specification; deleted from the t w1l specification; corrected the t rl specification (replaced with , applied note 12), and added more details to notes 4, 11 and 12. 3, 4 deleted the ds2480b (5v operation) master circuit from figure 4. 5 updated the package information section and added revision history . 11, 12 downloaded from: http:///

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